1) Field of the Invention
The Invention relates to a non-volatile memory cell with Twin MONOS structure, particularly aiming to high-speed application.
2) Description of the Related Art
Seiki Ogura et al introduced Twin MONOS original cell structure and its device operation in U.S. Pat. Nos. 6,255,166, 6,399,441 and 6,388,293, assigned to a common assignee and herein incorporated by reference in their entirety. A twin MONOS cell consists of a word gate as a select gate, a control gate pair on both sides of the word gate having an ONO memory element underneath, and a bit pair as source/drain diffusion on the other side of the control gates. The authors also provided two different array structures with fabrication methods; diffusion bit array in U.S. Pat. No. 6,248,633 and metal bit array in U.S. Pat. Nos. 6,469,935 and 6,531,350, assigned to a common assignee and herein incorporated by reference in their entirety. The diffusion bit array consists of a bit line, a control gate line having an ONO memory element underneath along the bit line, and a word gate connecting select gates crossing the bit line. It is convenient for high-density applications. The metal bit array consists of a word line running parallel to a control gate line and a bit line crossing the word line and control gate. Other related US patents include U.S. Pat. No. 6,631,088 to Ogura et al, U.S. Pat. No. 6,756,271 and U.S. Pat. No. 6,707,079 to Satoh et al, U.S. Pat. No. 6,759,290 to Ogura et al, U.S. Pat. No. 6,038,169 to Ogura et al and U.S. Pat. No. 6,011,725 to Eitan et al.